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?2012-2013 peregrine semiconductor corp. all rights reserved. page 1 of 20 document no. doc-16514-6 | www.psemi.com product description the pe43704 is a harp ? technology-enhanced, high linearity, 7-bit 50 ? rf digital step attenuator (dsa). it offers maximum power handling of 28 dbm up to 8 ghz and covers a 31.75 db attenuation range in 0.25 db, 0.5 db, or 1.0 db steps. the pe43704 is a pin-compatible version of pe43703. it provides multiple cmos control interfaces and an optional vss ext bypass mode to improve spurious performance. it maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. no blocking capacitors are required if dc voltage is not present on the rf ports. the pe43704 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. pe43704 figure 2. functional diagram features ?? harp? technology enhanced ?? safe attenuation state transitions ?? attenuation options: covers a 31.75 db range in 0.25 db, 0.5 db, or 1.0 db steps ?? 0.25 db monotonicity for 6 ghz ?? 0.50 db monotonicity for 7 ghz ?? 1.00 db monotonicity for 8 ghz ?? high power handling @ 8 ghz in 50 ? ?? 28 dbm cw ?? 31 dbm instantaneous power ?? high linearity ?? iip3 of 61 dbm ?? 1.8v/3.3v control logic ?? programming modes ?? direct parallel ?? latched parallel ?? serial ?? serial addressable ?? high-attenuation state @ power-up (pup) ?? esd performance ?? 1.5kv hbm on all pins product specification ultracmos ? rf digital step attenuator, 7-bit, 31.75 db with optional vss ext bypass mode 9 khz - 8 ghz figure 1. package type 32-lead 5x5 qfn doc-02161 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 2 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification table 1. electrical specifications: 0.25 db steps @ +25c, v dd = 2.3v to 5.5v, vss ext = 0v or v dd = 3.4v to 5.5v, vss ext = -3.4v (z s = z l = 50? ) unless otherwise noted notes: 1. the input 1db compression point is a linearity figure of merit. refer to table 5 for the rf input power p in (50 ? 2. to prevent negative voltage generat or spurs, supply ?3.4 volts to vss ext parameter condition frequency min typ max unit operating frequency 9 khz 6000 mhz as shown attenuation range 0.25 db step 0 ? 31.75 db insertion loss 9 khz ? 2 ghz 2 ghz ? 4 ghz 4 ghz ? 6 ghz 1.3 1.7 2.4 1.4 1.9 2.7 db db db attenuation error 9 khz 4 ghz + (0.15 + 3% of attenuation setting) - (0.1 + 1% of attenuation setting) db db 4 ghz ? 6 ghz + (0.15 + 5% of attenuation setting) - 0.15 db db 16 db ? 31.75 db attenuation settings 9 khz 4 ghz + (0.15 + 3% attenuation setting) - (0.1 + 1% of attenuation setting) db db 4 ghz ? 6 ghz + (0.25 + 5% of attenuation setting) 0.0 db db return loss input port 9 khz ? 4 ghz 4 ghz ? 6 ghz 20 15 db db return loss output port 9 khz ? 4 ghz 4 ghz ? 6 ghz 17 13 db db relative phase 0 db ? 31.75 db attenuation settings 9 khz ? 6 ghz 58 deg input 1db compression point 1 50 mhz ? 6 ghz 32 34 dbm iip3 two tones at +18 dbm, 20 mhz spacing 50 mhz ? 6 ghz 61 dbm typical spurious value 2 vss ext = 0v ?140 dbm rf trise/tfall 10% / 90% rf 600 ns settling time rf settled to within 0.05 db of final value 2 s switching time 50% ctrl to 90% or 10% rf 1.1 s 0 db ? 15.75 db attenuation settings logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 3 of 20 table 2. electrical specifications: 0.5 db steps @ +25c, v dd = 2.3v to 5.5v, vss ext = 0v or v dd = 3.4v to 5.5v, vss ext = -3.4v (z s = z l = 50? ) unless otherwise noted parameter condition frequency min typ max unit operating frequency 9 khz 7000 mhz as shown attenuation range 0.5 db step 0 ? 31.5 db insertion loss 9 khz ? 2 ghz 2 ghz ? 4 ghz 4 ghz ? 6 ghz 6 ghz ? 7 ghz 1.3 1.7 2.4 2.5 1.4 1.9 2.7 2.9 db db db db attenuation error 0 db ? 15.5 db attenuation settings 9 khz 4 ghz (0.15 + 3% of attenuation setting) - (0.1 + 2% of attenuation setting) db db 4 ghz ? 7 ghz + (0.25 + 5% of attenuation setting) - 0.25 db db 9 khz 4 ghz + (0.15 + 3% of attenuation setting) - (0.1 + 2% of attenuation setting) db db 4 ghz ? 7 ghz + (0.25 + 6% of attenuation setting) - (0.25 + 2.5% of attenuation setting) db db return loss input port 9 khz ? 4 ghz 4 ghz ? 7 ghz 20 16 db db return loss output port 9 khz ? 4 ghz 4 ghz ? 7 ghz 17 14 db db relative phase 0 db ? 31.5 db attenuation settings 9 khz ? 7 ghz 65 deg input 1db compression point 1 50 mhz ? 7 ghz 32 34 dbm iip3 two tones at +18 dbm, 20 mhz spacing 50 mhz ? 7 ghz 61 dbm typical spurious value 2 vss ext = 0v ?140 dbm rf trise/tfall 10% / 90% rf 600 ns settling time rf settled to within 0.05 db of final value 2 s switching time 50% ctrl to 90% or 10% rf 1.1 s 16 db ? 31.5 db attenuation settings notes: 1. the input 1db compression point is a linearity figure of merit. refer to table 5 for the rf input power p in (50 ? 2. to prevent negative voltage generat or spurs, supply ?3.4 volts to vss ext logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 4 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification table 3. electrical specifications: 1 db steps @ +25c, v dd = 2.3v to 5.5v, vss ext = 0v or v dd = 3.4v to 5.5v, vss ext = -3.4v (z s = z l = 50? ) unless otherwise noted parameter condition frequency min typ max unit operating frequency 9 khz 8000 mhz as shown attenuation range 1 db step 0 - 31 db insertion loss 9 khz ? 2 ghz 2 ghz ? 4 ghz 4 ghz ? 6 ghz 6 ghz ? 8 ghz 1.3 1.7 2.4 2.9 1.4 1.9 2.7 3.2 db db db db attenuation error 0 db ? 15 db attenuation settings 9 khz 4 ghz + (0.15 + 3% of attenuation setting) - (0.1 + 1% of attenuation setting) db db 4 ghz 7 ghz + (0.25 + 6% of attenuation setting) - (0.25 + 2% of attenuation setting) db db 7 ghz ? 8 ghz + (0.25 + 7% of attenuation setting) - (0.25 + 2% of attenuation setting) db db 9 khz 4 ghz + (0.15 + 3% of attenuation setting) - (0.1 + 1% of attenuation setting) db db 4 ghz 7 ghz + (0.25 + 6% of attenuation setting) - (0.25 + 3% of attenuation setting) db db 7 ghz ? 8 ghz + (0.25 + 7% of attenuation setting) - (0.25 + 4% of attenuation setting) db db return loss input port 9 khz ? 4 ghz 4 ghz ? 8 ghz 20 14.5 db db return loss output port 9 khz ? 4 ghz 4 ghz ? 8 ghz 17 12.5 db db relative phase 0 db ? 31 db attenuation settings 9 khz ? 8 ghz 80 deg input 1db compression point 1 50 mhz ? 8 ghz 32 34 dbm iip3 two tones at +18 dbm, 20 mhz spacing 50 mhz ? 8 ghz 61 dbm typical spurious value 2 vss ext = 0v ?140 dbm rf trise/tfall 10% / 90% rf 600 ns settling time rf settled to within 0.05 db of final value 2 s switching time 50% ctrl to 90% or 10% rf 1.1 s 16db ? 31 db attenuation settings notes: 1. the input 1db compression point is a linearity figure of merit. refer to table 5 for the rf input power p in (50 ? 2. to prevent negative voltage generat or spurs, supply ?3.4 volts to vss ext logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 5 of 20 figure 3. pin configuration (top view) pin # pin name description 1 n/c no connect 2 v dd supply voltage 3 p /s serial/parallel mode select 5, 6, 8-17, 19 gnd ground 7 rf1 1 rf1 port (rf input) 18 rf2 1 rf2 port (rf output) 20 vss ext 2 external vss negative voltage control 23 le serial interface latch enable input 24 clk serial interface clock input 25 si serial interface data input 26 c16 (d6) 3 parallel control bit, 16 db 27 c8 (d5) 3 parallel control bit, 8 db 28 c4 (d4) 3 parallel control bit, 4 db 29 c2 (d3) 3 parallel control bit, 2 db 30 c1 (d2) 3 parallel control bit, 1 db 31 c0.5 (d1) 3 parallel control bit, 0.5 db 32 c0.25 (d0) 3 parallel control bit, 0.25 db pad gnd exposed pad: ground for proper operation 4 a0 address bit a0 connection 22 a1 address bit a1 connection 21 a2 address bit a2 connection table 4. pin descriptions notes: 1. rf pins 7 and 18 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper operation if the 0v dc requirement is met 2. use vss ext (pin 20) to bypass and disable internal negative voltage generator. connect vss ext (pin 20) to gnd (vss ext = 0v) to enable internal negative voltage generator 3. ground c0.25, c0.5, c1 c2, c4, c8, c16 if not in use notes: 1. normal mode: connect vss ext (pin 20) to gnd (vss ext = 0v) to enable internal negative voltage generator 2. bypass mode: use vss ext (pin 20) to bypass and disable internal negative voltage generator 3. 100% duty cycle, all bands, 50 ? 4. pulsed, 5% duty cycle of 4620 s period, 50 ? table 5. operating ranges parameter symbol min typ max unit supply voltage (normal mode, vss ext = 0v) 1 v dd 2.3 5.5 v supply voltage (bypass mode, vss ext = -3.4v, v dd 3.4v for full spec. compliance) 2 v dd 2.7 3.4 5.5 v negative supply voltage (bypass mode) 2 vss ext -3.6 -2.4 v supply current (normal mode, vss ext = 0v) 1 i dd 130 200 a supply current (bypass mode, vss ext = -3.4v) 2 i dd 50 80 a digital input high v ih 1.17 3.6 v digital input low v il -0.3 0.6 v digital input current i ctrl 15 a rf input power, cw 3 9 khz < 50 mhz 50 mhz 8 ghz p max,cw see fig. 4 +28 dbm dbm operating temperature range t op -40 25 +85 c negative supply current (bypass mode, vss ext = -3.4v) 2 i ss -40 -16 a rf input power, pulsed 4 9 khz < 50 mhz 50 mhz 8 ghz p max,pulsed see fig. 4 +31 dbm dbm logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 6 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification table 7. latch and clock specifications latch enable function 0 shift register clocked contents of shift register transferred to attenuator core shift clock x electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. switching frequency the pe43704 has a maximum 25 khz switching rate when the internal negative voltage generator is used (pin 20 = gnd). the rate at which the pe43704 can be switched is only limited to the switching time ( tables 1-3 ) if an external negative supply is provided (pin 20 = vss ext ). switching frequency is defined to be the speed at which the dsa can be toggled across attenuation states. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. optional external vss control (vss ext ) for proper operation, the vss ext control pin must be grounded or tied to the vss voltage specified in table 5 . when the vss ext control pin is grounded, fets in the switch are biased with an internal voltage generator. for applications that require the lowest possible spur performance, vss ext can be applied externally to bypass the internal negative voltage generator. moisture sensitivity level the moisture sensitivity level rating for the pe43704 in the 5x5 qfn package is msl1. safe attenuation state transitions the pe43704 features a novel architecture to provide safe transition behavior when changing attenuation states. when rf input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing control. table 6. absolute maximum ratings parameter/condition symbol min max unit supply voltage v dd -0.3 5.5 v digital input voltage v ctrl -0.3 3.6 v rf input power, max p max,abs +34 dbm storage temperature range t st -65 +150 c esd voltage hbm 1 , all pins v esd,hbm 1500 v esd voltage mm 2 , all pins v esd,mm 200 v esd voltage cdm 3 , all pins v esd,cdm 250 v exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. notes: 1. human body model (mil-std 883 method 3015) 2. machine model (jedec jesd22-a115) 3. charged device model (jedec jesd22-c101) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 7 of 20 figure 4. power de-rating curve (50 ? , -40 c to 85c ambient) 0 5 10 15 20 25 30 35 1 10 100 1,000 10,000 100,000 1,000,000 10,000,000 input ? power ? (dbm) frequency ? (khz) max.? rf ? input ? power, ? cw ? & ? pulsed ? (9k ?\? < ? 50mhz) max.? rf ? input ? power, ? cw ? (50m ?\? 8ghz) max.? rf ? input ? power, ? pulsed ? (50m ?\? 8ghz) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 8 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification table 9. serial attenuation word truth table parallel control setting attenuation setting rf1-rf2 d6 d5 d4 d3 d2 d1 d0 l l l l l l l reference i.l. l l l l l l h 0.25 db l l l l l h l 0.5 db l l l l h l l 1 db l l l h l l l 2 db l l h l l l l 4 db l h l l l l l 8 db h l l l l l l 16 db h h h h h h h 31.75 db table 8. parallel truth table attenuation word d7 d6 d5 d4 d3 d2 d1 d0 (lsb) l l l l l l l l reference i.l. l l l l l l l h 0.25 db l l l l l h l l 1 db l l l l h l l l 2 db l l l h l l l l 4 db l l h l l l l l 8 db l h l l l l l l 16 db l h h h h h h h 31.75 db attenuation setting rf1-rf2 l l l l l l h l 0.5 db address word address setting a7 (msb) a6 a5 a4 a3 a2 a1 a0 x x x x x l l l 000 x x x x x l l h 001 x x x x x l h l 010 x x x x x l h h 011 x x x x x h l l 100 x x x x x h l h 101 x x x x x h h l 110 x x x x x h h h 111 table 10. serial address word truth table table 11. serial-addressable register map q15 q14 q13 q12 q11 q10 a7 a6 a5 a4 a3 a2 q9 q8 q7 q6 q5 q4 a1 a0 d7 d6 d5 d4 q3 q2 q1 q0 d3 d2 d1 d0 address word attenuation word lsb (first in) msb (last in) bits can either be set to logic high or logic low attenuation word is derived directly from the attenuation value. for example, to program the 18.25 db state at address 3: address word: xxxxx011 attenuation word: multiply by 4 and convert to binary 4 * 18.25 db 73 01001001 serial input: xxxxx01101001001 d7 must be set to logic low logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 9 of 20 programming options parallel/serial selection either a parallel or serial -addressable interface can be used to control the pe43704. the p /s bit provides this selection, with p /s = low selecting the parallel interface and p/s = high selecting the serial- addressable interface. parallel mode interface the parallel interface c onsists of seven cmos- compatible control lines that select the desired attenuation state, as shown in table 8 . the parallel interface timing requirements are defined by figure 6 (parallel interface timing diagram), table 13 (parallel and direct interface ac characteristics) and switching time ( tables 1-3 ). for latched -parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low ( per figure 6) to latch new attenuati on state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will change device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). serial interface the serial-addressable interfac e is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. the 16-bits make up two words comprised of 8- bits each. the first word is the attenuation word, which controls the state of the dsa. the second word is the address word, which is compared to the static (or programmed) logical states of the a0, a1 and a2 digital inputs. if there is an addr ess match, the dsa changes state; otherwise its current state will remain unchanged. figure 5 illustrates an example timing diagram for programming a state. it is required that all parallel control inputs be grounded when the dsa is used in serial-addressable mode. the serial-interface is c ontrolled using three cmos- compatible signals: serial-in (si), clock (clk), and latch enable (le). the si and clk inputs allow data to be serially entered into the shift register. serial data is clocked in lsb first, beginning with the attenuation word. the shift register must be loaded while le is held low to prevent the attenuator value from changing as data is entered. t he le input should then be toggled high and brought low again, latching the new data into the dsa. attenuation word and address word truth tables are listed in table 9 and table 10 . a programming example of the serial register is illustrated in table 11. the serial timing diagram is illustrated in figure 5. power-up control settings the pe43704 will always initialize to the maximum attenuation setting (31.75 db) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. in direct -parallel mode, the dsa can be preset to any state within the 31.75 db range by pre-setting the parallel control pins prior to power- up. in this mode, there is a 400- s delay between the time the dsa is powered-up to the time the desired state is set. during this power-up delay , the device attenuates to the maximum attenuation setting (31.75 db) before defaulting to the us er defined state. if the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). dynamic operation between serial and parallel programming modes is possible. if the dsa powers up in serial mode ( p /s = high), all the parallel control inputs di[6:0] must be set to logic low. prior to toggling to parallel mode, the dsa must be programmed serially to ensure d[7] is set to logic low. if the dsa powers up in either latched or direct- parallel mode, all parallel pi ns di[6:0] must be set to logic low prior to toggling to serial-addressable mode ( p /s = high), and held low until the dsa has been programmed serially to ensure bit d[7] is set to logic low. the sequencing is only required once on power-up. once completed, the dsa may be toggled between serial and parallel programming modes at will. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 10 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification v dd = 3.4v or 5.0v, -40c < t a < 85c, unless otherwise specified v dd = 3.4v or 5.0v, -40c < t a < 85c, unless otherwise specified figure 5. serial timing diagram figure 6. latched-parallel/direct-parallel timing diagram parameter symbol min max unit serial clock frequency f clk - 10 mhz serial clock high time t clkh 30 - ns serial clock low time t clkl 30 - ns last serial clock rising edge setup time to latch enable rising edge t lesu 10 - ns latch enable min. pulse width t lepw 30 - ns serial data setup time t sisu 10 - ns serial data hold time t sih 10 - ns parallel data setup time t disu 100 - ns parallel data hold time t dih 100 - ns address setup time t asu 100 - ns address hold time t ah 100 - ns parallel/serial setup time t pssu 100 - ns parallel/serial hold time t psh 100 - ns digital register delay (internal) t pd - 10 ns symbol parameter min max unit t lepw latch enable minimum pulse width 30 - ns t disu parallel data setup time 100 - ns t dih parallel data hold time 100 - ns t pssu parallel/serial setup time 100 - ns t psih parallel/serial hold time 100 - ns t pd digital register del ay (internal) - 10 ns t dipd digital register delay (internal, direct mode only) - 5 ns valid t disu t dih di[6:0] le p/s t pssu t psh t lepw valid do[6:0] t dipd t pd table 13. parallel and direct interface ac characteristics table 12. serial interface ac characteristics d[7] must be set to logic low bits can either be set to logic high or logic low d[0] d[1] d[2] d[3] d[4] d[5] d[7] t sisu t clkl t lepw t sih t clkh si clk le p/s t lesu t pssu t psih valid t disu t pd t dih d[6] di[6:0] do[6:0] logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 11 of 20 figure 7. 0.25 db step attenuation vs. frequency* typical performance data, 0.25 db step @ 25c and v dd = 3.4v unless otherwise specified figure 8. 0.25 db step, actual vs. frequency figure 9. 0.25 db major state bit error vs. attenuation setting figure 10. 0.25 db attenuation error vs. frequency * monotonicity is held so long as step- attenuation does not cross below ?0.25 db \ 0.25 \ 0.125 0 0.125 0.25 0 4 8 12 16 20 24 28 32 step ? attenuation ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 actual ? attenuation ? (db) ideal ? attenuation ? (db) 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz \ 0.5 0 0.5 1 1.5 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz \ 0.5 0 0.5 1 1.5 0123456 attenuation ? error ? (db) frequency ? (ghz) 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 12 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification typical performance data, 0.5 db step @ 25c and v dd = 3.4v unless otherwise specified figure 11. 0.5 db step attenuation vs. frequency* figure 12. 0.5 db step, actual vs. frequency figure 13. 0.5 db major state bit error vs. attenuation setting figure 14. 0.5 db attenuation error vs. frequency * monotonicity is held so long as step- attenuation does not cross below ?0.5 db 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 actual ? attenuation ? (db) ideal ? attenuation ? (db) 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz \ 0.5 0 0.5 1 1.5 01234567 attenuation ? error ? (db) frequency ? (ghz) 0.5db 1db 2db 4db 8db 16db 31.5db \ 0.5 \ 0.25 0 0.25 0.5 0 4 8 121620242832 step ? attenuation ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz \ 0.5 0 0.5 1 1.5 0 4 8 121620242832 attenuation ? error ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 13 of 20 typical performance data, 1 db step @ 25c and v dd = 3.4v unless otherwise specified figure 16. 1 db step, actual vs. frequency figure 15. 1 db step attenuation vs. frequency* figure 17. 1 db major state bit error vs. attenuation setting * monotonicity is held so long as step- attenuation does not cross below ?1.0 db 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 actual ? attenuation ? (db) ideal ? attenuation ? (db) 0.9ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz \ 1 \ 0.5 0 0.5 1 1.5 012345678 attenuation ? error ? (db) frequency ? (ghz) 1db 2db 4db 8db 16db 31db \ 1 \ 0.5 0 0.5 1 0 4 8 12 16 20 24 28 32 step ? attenuation ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 14 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification figure 18. 1 db attenuation error vs. frequency figure 19. insertion loss vs. temperature typical performance data, 1 db step @ 25c and v dd = 3.4v unless otherwise specified figure 20. input return loss vs. attenuation setting figure 21. output return loss vs. attenuation setting \ 5 \ 4.5 \ 4 \ 3.5 \ 3 \ 2.5 \ 2 \ 1.5 \ 1 \ 0.5 0 0123456789 insertion ? loss ? (db) frequency ? (ghz) \ 40c 25c 85c \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db \40 \35 \30 \25 \20 \15 \10 \5 0 0123456789 return ? loss ? (db) frequency ? (ghz) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db \ 1 \ 0.5 0 0.5 1 1.5 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 15 of 20 typical performance data, 1 db step @ 25c and v dd = 3.4v unless otherwise specified figure 22. input return loss vs. temperature for 16 db attenuation setting figure 23. output return loss vs. temperature for 16 db attenuation setting \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) \ 40c 25c 85c \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) \ 40c 25c 85c logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 16 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification figure 24. relative phase error vs. attenuation setting figure 25. relative phase error for 31.75 db attenuation setting vs. frequency typical performance data @ 25c and v dd = 3.4v unless otherwise specified figure 26. attenuation error @ 900 mhz vs. temperature figure 27. attenuation error @ 1800 mhz vs. temperature figure 28. attenuation error @ 3000 mhz vs. temperature figure 29. iip3 vs. attenuation setting 0 20 40 60 80 100 012345678 relative ? phase ? error ? (deg) frequency ? (ghz) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 0 10 20 30 40 50 60 70 \ 40 25 85 relative ? phase ? error ? (deg) temperature ? (deg ? c) 0.9ghz 1.8ghz 2ghz 3ghz 4ghz 5ghz 6ghz \ 0.5 \ 0.25 0 0.25 0.5 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) \ 40c 25c 85c \ 0.5 \ 0.25 0 0.25 0.5 0.75 0 4 8 121620242832 attenuation ? error ? (db) attenuation ? setting ? (db) \ 40c 25c 85c \ 0.5 \ 0.25 0 0.25 0.5 0.75 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) \ 40c 25c 85c 60 62 64 66 68 70 72 74 2345678 input ? ip3 ? (dbm) ?? frequency ? (ghz) 0db 8db 16db logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 17 of 20 evaluation kit the digital attenuator evaluation board (evb) was designed to ease customer evaluation of the pe43704 digital step attenuator. pe43704 evb supports direct-parallel, latched-parallel, and serial modes. evaluation kit setup connect the evb with the usb dongle board and usb cable as shown in figure 30. direct-parallel programming procedure direct-parallel programming is suitable for manual operation without software programming. for manual direct-parallel programming, position the parallel/serial (p/s) select switch to the parallel (or left) position. the le pin of j1 (pin 15) must be tied to high voltage. switches d0?d6 are sp3t switches that enable the user to manually program the parallel bits. when d0?d6 are toggled to the ?high? position, logic high is presented to the parallel input. when toggled to the ?low? position, logic low is presented to the parallel input. setting d0?d6 to the ?auto? position presents as open, which is set for software programming of latched- parallel and serial mode. table 8 depicts the parallel programming truth table. latched-parallel programming procedure for automated latched-parallel programming, connect the usb dongle board and cable that is provided with the evaluation kit (evk) from the usb port of the pc to the j1 header of the pe43704 evb, and set the d0?d6 sp3t switches to the ?auto? position. position the parallel/serial (p/s) select switch to the parallel (or left) position. the evaluation software is written to operate the dsa in parallel mode. ensure that the software gui is set to latched-parallel mode. use the software gui to enable the desired attenuation state. the software gui automatically programs the dsa each time an attenuation state is enabled. serial-addressable programming procedure for automated serial programming, connect the usb dongle board and cable that is provided with the evaluation kit (evk) from the usb port of the pc to the j1 header of the pe43704 evb, and set the d0?d6 sp3t switches to the ?auto? toggle position. position the parallel/serial (p/s) select switch to the serial (or right) position. prior to programming, the user must define an address setting using the hdr4 header pin. jump the middle row of pins on the hdr4 header (a0?a2) to the lower row of pins to set logic low, or jump the middle row of pins to the upper row of pins to set logic high. if the hdr4 pins are left open, then 000 becomes the default address. the software gui is written to operate the dsa in serial mode. use the software gui to enable each setting to the desired attenuation state. the software gui automatically programs the dsa each time an attenuation state is enabled. figure 31. evaluation board layout prt-13505 figure 30. evaluation kit a0 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 18 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification figure 32. evaluation board schematic 2. caution: contains parts and asse mblies susceptible notes: to damage by electrostatic discharge (es d) 1. use prt-13505-01 pcb. z=50 oh m z=50 oh m z=50 oh m de-embeding trac e dni vdd 3 1 2 4 d3 5 4 6 p/s c6 100pf 3 1 2 4 d4 c4 100pf 3 1 2 4 d5 c3 100pf 3 1 2 4 d6 3 1 2 4 d1 c2 100pf 3 1 2 4 d2 c5 100pf 21 43 65 87 10 9 12 11 14 13 16 15 j1 he ader16 1 gnd 2 vdd 3 ps 4 a0 5 gnd 6 gnd 7 rf1 8 gnd 9 gnd 10 gnd 11 gnd 12 gnd 13 gnd 14 gnd 15 gnd 16 gnd 17 gnd 18 rf2 20 vss 19 gnd 21 a2 22 a1 23 le 24 clk 25 si 26 c16 27 c8 28 c4 29 c2 30 c1 31 cp5 32 cp25 u1 ds a_50ohm_5x5_mlpq32 r4 0ohm 3 1 2 4 d0 c9 0.1f c10 100pf 1 2 r3 dni 12 r1 dni r2 0ohm c1 100pf 1 2 3 4 hdr2 header_4 c11 100pf c7 100pf c8 0.1f c12 100pf 1 2 j4 142-0761-881/891 1 2 j10 142-0761-881/891 1 2 j11 142-0761-881/891 1 2 j5 142-0761-881/891 a0_2 a0 a1_2 a1 a2_2 a2 a2_1 vdd a1_1 vdd a0_1 vdd hdr4 he ader3x3 1 1 2 2 hdr1 header 1x2 1 1 2 2 hdr3 header 1x2 c0_5 c1 c16/data vss vdd_dig c8clk c4 c2 co_25 vdd_dig le vdd_dig vdd doc-16527 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
pe43704 product specification ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-16514-6 | www.psemi.com page 19 of 20 top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin#1corner 5.00 5.00 3.300.05 3.300.05 3.50 3.50 0.50 0.240.05 (x32) 0.3750.05 (x32) 0.203 ref. 0.05 0.90 max 0.575 (x32) 0.290 (x32) 3.35 5.20 3.35 5.20 0.50 (x28) detail a 1 8 9 16 17 24 25 32 figure 33. package drawing 32-lead 5x5 qfn figure 34. top marking specification doc-01872 43704 yyww zzzzzz 17-0091 = pin 1 designator yyww = date code, last two digits of the year and work week zzzzzz = six digits of the lot number logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
document no. doc-16514-6 | ultracmos ? rfic solutions page 20 of 20 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe43704 product specification device orientation in tape top of device pin 1 tape feed direction table 14. ordering information figure 35. tape and reel drawing order code description package shipping method pe43704mlca-z pe43704 digital step attenuator 32-lead 5x5 mm qfn 3000 units / t&r ek43704-11 pe43704 evaluation ki t evaluation kit 1 / box notes: 1. 10 sprocket hole pitch cumulative tolerance .02 2. camber not to exceed 1 mm in 100 mm 3. material: ps + c 4. ao and bo measured as indicated 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole ao = 5.25 mm bo = 5.25 mm ko = 1.1 mm advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com

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